Preface
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|
VII |
Chapter 1 Digital Designs with EDA and FPGA
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|
1 |
| 1.1. Overview |
|
3 |
| 1.2. Register Transfer Level |
|
5 |
| 1.3. Electronic Design Automation and Hardware Description Language |
|
6 |
| 1.4. Field Programmable Gate Arrays |
|
8 |
| 1.5. DE1, DE1-SOC and DE2-115 Boards |
|
9 |
| 1.6. Exercises |
|
11 |
| |
|
|
Chapter 2 VHDL Primers
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|
13 |
| 2.1. Basic Modeling |
|
14 |
| 2.1.1. Lexical Elements |
|
14 |
| 2.1.2. VHDL Data Types |
|
16 |
| 2.2. Packages in IEEE Library |
|
23 |
| 2.2.1. Multi-Valued Logic System |
|
24 |
| 2.2.2. Logic Operators/Functions |
|
26 |
| 2.2.3. Arithmetic Operators/Functions |
|
27 |
| 2.3. Concurrent Statements |
|
27 |
| 2.3.1. Signal Assignments and Operators |
|
28 |
| 2.3.2. WHEN-ELSE |
|
28 |
| 2.3.3. Component Instantiation |
|
32 |
| 2.3.4. Process |
|
35 |
| 2.4. Sequential Statements |
|
36 |
| 2.4.1. Assignments and Functions |
|
36 |
| 2.4.2. IF Statements |
|
36 |
| 2.4.3. CASE Statements |
|
37 |
| 2.5. Exercises |
|
40 |
| |
|
|
Chapter 3 RTL Digital Designs
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|
46 |
| 3.1. Combinational RTL Components |
|
47 |
| 3.1.1. Signals and Numbers |
|
47 |
| 3.1.2. Multiplexers |
|
48 |
| 3.1.3. Adders |
|
57 |
| 3.1.4. Multipliers |
|
66 |
| 3.1.5. Comparators |
|
67 |
| 3.2. Sequential RTL Components |
|
70 |
| 3.2.1. VHDL Structure for Sequential Digital Circuits |
|
70 |
| 3.2.2. Registers |
|
74 |
| 3.2.3. Shift Registers |
|
76 |
| 3.2.4. Counters |
|
79 |
| 3.3. Memory Components |
|
84 |
| 3.3.1. FPGA's Built-in RAMs |
|
84 |
| 3.3.2. ROMs |
|
87 |
| 3.3.3. SRAM |
|
89 |
| 3.4. Finite State Machines |
|
90 |
| 3.5. Exercises |
|
94 |
| |
|
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Chapter 4 Design of Digital Systems
|
|
99 |
| 4.1. Digital System Modeling |
|
100 |
| 4.1.1. Functional Block Diagrams |
|
101 |
| 4.1.2. State Diagram |
|
102 |
| 4.1.3. Flowchart |
|
102 |
| 4.1.4. FSM VHDL Infrastructure |
|
103 |
| 4.2. Design Example I: Sequence Detector |
|
106 |
| 4.2.1. Combinational Case |
|
106 |
| 4.2.2. Single Event Part I |
|
107 |
| 4.2.3. Single Event Part II |
|
109 |
| 4.2.4. Complex Sequence |
|
110 |
| 4.2.5. Sequence with Time Constraint |
|
112 |
| 4.3. Design Example II: Stopwatch |
|
122 |
| 4.3.1. Frequency Generator |
|
122 |
| 4.3.2. BCD Counter |
|
124 |
| 4.3.3. Controller |
|
127 |
| 4.3.4. Hex-to-Sevenseg and Debounce |
|
132 |
| 4.3.5. Stopwatch Design Version 1 |
|
135 |
| 4.3.6. Stopwatch Design Version 2 |
|
136 |
| 4.4. Exercises |
|
142 |
| |
|
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Chapter 5 Personal System/2 (PS/2) Keyboard
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|
147 |
| 5.1. PS/2 Protocol |
|
148 |
| 5.1.1. Physical Connectors |
|
148 |
| 5.1.2. Serial Data Format |
|
149 |
| 5.1.3. Keyboard Interface Design |
|
150 |
| 5.2. Keyboard Scan Code |
|
154 |
| 5.2.1. Make and Break Codes |
|
155 |
| 5.2.2. Simple Interface Design Example |
|
155 |
| 5.3. Handshaking and Decision Makings |
|
159 |
| 5.3.1. Two-Wire Handshaking |
|
159 |
| 5.3.2. Handshaking with Keyboard Interface |
|
160 |
| 5.3.3. Using Shift Register to Detect Break Codes |
|
165 |
| 5.4. Ticker Display Example |
|
167 |
| 5.4.1. Modified Hex-to-Sevenseg |
|
169 |
| 5.4.2. Slow Clock Generator |
|
170 |
| 5.4.3. Keyboard Command Interpreter |
|
171 |
| 5.4.4. Ticker Display Controller |
|
177 |
| 5.4.5. Complete Design |
|
180 |
| 5.5. Exercises |
|
182 |
| |
|
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Chapter 6 Video Graphics Array (VGA)
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|
188 |
| 6.1. VGA Interface Design |
|
191 |
| 6.1.1. VGA Timing Specifications |
|
191 |
| 6.1.2. Phase Lock Loop |
|
194 |
| 6.1.3. VGA Hardware Supports on DE Boards |
|
197 |
| 6.1.4. Basic VGA Interface |
|
200 |
| 6.1.5. Screen Test Circuit |
|
203 |
| 6.2. Video Memory |
|
208 |
| 6.2.1. General Organization |
|
209 |
| 6.2.2. Color Depth and Memory Space Utilization |
|
210 |
| 6.2.3. VGA Interface with Video RAM Design |
|
212 |
| 6.2.4. Bouncing Ball Example |
|
217 |
| 6.3. Animation with Keyboard Controls |
|
225 |
| 6.3.1. Design Overview |
|
225 |
| 6.3.2. Keyboard Handler |
|
226 |
| 6.3.3. Drawing Borders and Initial Paddle |
|
227 |
| 6.3.4. Collision Detections |
|
229 |
| 6.3.5. Main FSM Design |
|
231 |
| 6.4. Exercises |
|
242 |
| |
|
|
Chapter 7 Text Video
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|
246 |
| 7.1. VGA Interface with Hardware Font Table |
|
247 |
| 7.1.1. Hardware Organization |
|
247 |
| 7.1.2. Bitmap Font Construction |
|
249 |
| 7.1.3. ROM: 1-Port |
|
251 |
| 7.1.4. Design of VGA Interface with Built-in Font Table |
|
252 |
| 7.1.5. Text Video Screen Test |
|
256 |
| 7.1.6. In-System Memory Content Editor |
|
259 |
| 7.2. Text Terminal Design Example |
|
259 |
| 7.2.1. Design Overview |
|
261 |
| 7.2.2. Converting Scan Codes to ASCII Codes |
|
262 |
| 7.2.3. FSM Design |
|
263 |
| 7.2.4. VHDL Codes |
|
266 |
| 7.3. Multi-Colored Displays |
|
273 |
| 7.3.1. Colored Text |
|
273 |
| 7.3.2. Multiple Lookup tables |
|
280 |
| 7.3.3. Single Lookup Table |
|
284 |
| 7.4. Exercises |
|
292 |
| |
|
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Chapter 8 Digital Audio
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|
296 |
| 8.1. Audio Interface Design |
|
300 |
| 8.1.1. I2
C Controller |
|
301 |
| 8.1.2. Bit Clock and Left/Right Clock |
|
311 |
| 8.1.3. Digital Audio Receiver/Transmitter |
|
312 |
| 8.1.4. Echo Audio Effect |
|
317 |
| 8.2. Digital Audio Signal Generations |
|
323 |
| 8.2.1. Wavetable Synthesizer |
|
323 |
| 8.2.2.Random Number Generators for White Noise Generations |
|
328 |
| 8.2.3. Digital Audio Generator Test Circuit |
|
332 |
| 8.3. Finite Impulse Response Filter |
|
334 |
| 8.3.1. Altera's FIR Compiler |
|
335 |
| 8.3.2. Avalon Bus Interface |
|
338 |
| 8.3.3. FIR Filter Test Circuit |
|
340 |
| 8.4. Exercises |
|
343 |
| |
|
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Chapter 9 Advanced Digital Design Examples
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|
349 |
| 9.1. PS/2 Mouse Interface Design |
|
350 |
| 9.1.1. PS/2 Transmitter and Receiver |
|
352 |
| 9.1.2. PS/2 Protocol for Mouse |
|
355 |
| 9.1.3. Data Packet |
|
358 |
| 9.2. Video Interface with Full VGA Resolution |
|
365 |
| 9.2.1. SRAM Interface |
|
366 |
| 9.2.2. Hardware Mouse Cursor |
|
369 |
| 9.2.3. Video memory Constructed from Two Video RAMs |
|
374 |
| 9.3. Mandelbrot Set |
|
379 |
| 9.3.1. Mandelbrot Calculations |
|
379 |
| 9.3.2. Zoom Functions |
|
381 |
| 9.3.3. Fixed-Point Arithmetic |
|
383 |
| 9.3.4. Mandelbrot with Fixed-Point Arithmetic Circuits |
|
385 |
| 9.4. Mandelbrot with Double Precision Floating-Point Numbers |
|
390 |
| 9.4.1. Floating-Point Number Standard |
|
390 |
| 9.4.2. Altera's FP Megafunctions |
|
392 |
| 9.4.3. Datapaths |
|
395 |
| 9.4.4. Mandelbrot with Floating-Point Arithmetic Circuits |
|
398 |
| 9.5. Multiple Clock Domains |
|
408 |
| 9.5.1. DE1 and DE2-115 Examples |
|
408 |
| 9.5.2. DE1-SOC Examples |
|
410 |
| 9.5.3. Hardware Resource Utilizations |
|
410 |
| 9.6. Exercises |
|
412 |
| |
|
|
Chapter 10 More About VHDL
|
|
416 |
| 10.1. Compiler Directives |
|
417 |
| 10.1.1. ASSERT and REPORT |
|
418 |
| 10.1.2. Data Related |
|
419 |
| 10.1.3. Simulation Related |
|
420 |
| 10.2. Attributes |
|
421 |
| 10.2.1. For Scalar Types |
|
422 |
| 10.2.2. For Array Types |
|
422 |
| 10.2.3. For Signals |
|
423 |
| 10.2.4. For Entities |
|
423 |
| 10.3. Synthesizable Statements |
|
424 |
| 10.3.1. Combinational Ststements |
|
424 |
| 10.3.2. Sequential Statements |
|
429 |
| 10.3.3. Configuration Specifications |
|
431 |
| 10.4. Iterative Structures |
|
431 |
| 10.4.1. FOR-GENERATE |
|
431 |
| 10.4.2. IF-GENERATE |
|
433 |
| 10.4.3. LOOP |
|
437 |
| 10.5. Subprograms |
|
441 |
| 10.5.1 Functions |
|
441 |
| 10.5.2. Procedures |
|
443 |
| 10.6. Library and Package |
|
445 |
| 10.6.1. Package Declaration |
|
445 |
| 10.6.2. Create a Package |
|
449 |
| 10.6.3. Create a Library |
|
451 |
| 10.7. Exercises |
|
454 |
| |
|
|
APPENDIX A Operators and Functions Overloading
|
|
458 |
| A.1. From STD_LOGIC_1164 |
|
459 |
| A.2. From NUMERIC_STD |
|
459 |
| |
|
|
APPENDIX B IEEE Packages
|
|
462 |
| B.1. Standard (Built-In) |
|
463 |
| B.2. STD_LOGIC_1164 |
|
465 |
| B.3. NUMERIC_STD |
|
470 |
| B.4. NUMERIC_BIT |
|
473 |
| |
|
|
APPENDIX C Additional EDA Tools
|
|
479 |
| C.1. Programmer |
|
480 |
| C.2. ModelSim-Altera |
|
486 |
| C.3. SignalTap II Logic Analyzer |
|
495 |
| |
|
|
INDEX
|
|
501 |
